1. Field of the Invention
The present invention relates to a semiconductor device including insulated gate field effect transistors (hereinafter referred to as MISFET) and a method of manufacturing the same.
2. Description of the Related Art
An integrated circuit having high performance is demanded, and high-speed operation is also demanded for a complementary circuit which is one of basic circuits. For the high-speed operation of the complementary circuit, a method in which a channel length of MISFET being a basic element of the complementary circuit is decreased by a fine device technique has been used. Since the fine device structure involves formation of thin films for a gate insulating film and a gate electrode film of MISFET, correspondence to the high-speed operation is reaching a limit in a material which is conventionally used. Therefore, recently new materials and new element structures and manufacturing methods applying the new material have been developed.
For example, since polysilicon generally used as the material of the gate electrode has high resistivity, metal or metal silicide is used instead of polysilicon. However, these materials have a drawback that the materials are inferior in heat resistance to polysilicon.
On the other hand, there is a damascene gate process in which the gate insulating film and the gate electrode are formed after a high-temperature process is carried out. In the damascene gate process, source and drain regions are formed after an oxide film and a polysilicon film which become a dummy are previously formed in an intended gate region. Then, the films which become the dummy are removed and the gate insulating film and the gate electrode made of metal or metal silicide are buried in the removed region.
In the case that the above-described method is applied to the integrated circuit including the complementary circuit, work functions of the gate electrodes become the same when the same metals are used for the gate electrodes of an N-channel MISFET and a P-channel MISFET, so that it becomes difficult to control each threshold voltage to a proper value on circuit operation. Accordingly, it is necessary to provide the different gate electrode materials for the N-channel MISFET and the P-channel MISFET.
For example, in Japanese Patent No. 3264264 (Jpn. Pat. Appln. KOKAI publication No. 2000-252370), the polysilicon films which become the dummies are formed on a semiconductor substrate and source and drain layers are formed. Then, the dummy films are removed and the gate electrodes having the different materials for the N-channel MISFET and the P-channel MISFET are buried in the removed regions respectively. In the method, each threshold voltage of the N-channel MISFET and the P-channel MISFET is controlled to the proper value on the circuit operation, thereby obtaining the integrated circuit having high performance.
For example, it is assumed that a first gate electrode material is used for the N-channel MISFET and a second gate electrode material is used for the P-channel MISFET. In this case, after the first gate electrode material is formed over a surface of the semiconductor substrate, the first gate electrode material for the intended P-channel MISFET region is removed by etching, leaving the first gate electrode material for the intended N-channel MISFET region. Then, after a surface treatment, a cleaning pretreatment for a next process, and the like are carried out, the second gate electrode material is formed only in the intended P-channel MISFET region.
Therefore, in the process in which the first gate electrode material is removed by the etching, the gate insulating film of the P-channel MISFET is always exposed to etching species such as a gas or chemicals, whereby unwanted chemical reaction occurs at the substrate surface. Further, even in the subsequent cleaning processes, the similar reaction is caused by the chemicals for removing metal contamination and the like.
In today's situation in which the fine device structure of the integrated circuit remarkably proceeds, the gate insulating film is thinned to such an extent that the gate insulating film can be counted by an atomic layer. Accordingly, in the case that the gate insulating film is exposed to the gas or chemicals, even if the etching species is selected so that the etching of the gate insulating film is not generated in a macroscopic level, there occurs a problem that uniformity of the gate insulating film is degraded in a microscopic level.
In the integrated circuit, it is important that electrical insulating properties of the gate insulating film in a manufacturing step are prevented from the degradation in long time use of a product with time to secure the reliability. The above-described non-uniformity would become the large problem because it acts as a factor for providing an adverse effect and variation to the reliability.